vivado-red-mcp — Vivado MCP server, Red Pitaya edition

An MCP server that lets an AI assistant such as Claude drive AMD/Xilinx Vivado directly: create projects, build block designs, synthesize, implement, simulate, read timing/utilization reports and generate bitstreams — without opening the Vivado GUI.

It has first-class support for the Red Pitaya STEMlab 125-14 (Zynq xc7z010clg400-1): you can go from a natural-language description to a .bit.bin running on the board, using either pure RTL or the official RedPitaya-FPGA PS+PL (ARM + FPGA) backbone, and deploy it over SSH.

Forked from coreyhahn/vivado_mcp and heavily extended (93 tools): block design / IP Integrator, IP catalog, Hardware Manager, advanced reports, Red Pitaya RTL and PS+PL flows, SSH deploy.

Current version: 0.5.0 — see What's new and CHANGELOG.md.

Not to be confused with the unrelated vivado-mcp package on PyPI. This project is vivado-red-mcp: Python module vivado_red_mcp, command vivado-red-mcp.

Contents

• What it can do
• Tested with
• Requirements
• Installation
• First steps
• Red Pitaya
• What's new in 0.5.0
• Troubleshooting
• Available tools
• Architecture
• License

What it can do

• Persistent Vivado session — one Vivado process in Tcl mode is kept alive, so commands don't pay the 20–30 s startup each time.
• Projects and design flow — create/open projects, add HDL and XDC files, synthesis, implementation, bitstream, run strategies.
• Block design (IP Integrator) — ports, IP cores, RTL module cells, nets, PS7 presets, validation, wrapper generation.
• Reports — timing (WNS/TNS/WHS/THS), utilization, clocks, power, DRC, methodology, QoR; returned as parsed values, not just raw text.
• Simulation (xsim) — behavioral and post-synthesis/implementation, read signal values, breakpoints.
• Red Pitaya — one-shot RTL build, full PS+PL build from the official RedPitaya-FPGA repo, bundled board constraints, .bit.bin generation, SSH deploy.
• Raw Tcl — anything not covered by a tool can be run as Tcl (multi-line scripts supported).

Tested with

The RedPitaya-FPGA tutorials in prj/Examples (Led_blink, Knight_rider, Stopwatch, Frequency_counter) build to a bitstream through the server. Led_blink and Knight_rider rebuilt from scratch with MCP tools only produce byte-identical bitstreams to the tutorials' own scripts.

Requirements

1. Python 3.10+
2. AMD Vivado (the free edition is enough for the Red Pitaya xc7z010). When installing, you only need Vivado and, under devices, SoCs → Zynq-7000; Vitis Model Composer and DocNav are not needed.
3. A Vivado license file — also for the free edition on 2025.x/2026.x. Without it Vivado refuses to start (a valid license was not found):
   • open the Vivado License Manager (<Vivado>/bin/vlm.bat on Windows, vlm on Linux);
   • Obtain License → on the AMD site tick Vivado Basic Tier License, Node Locked License (no charge, no expiry) → *Generate Node-

... View full README on GitHub