mcp-server-edif

MCP server and CLI tool for querying EDIF (Electronic Design Interchange Format) netlist files.

Load an EDIF/EDF file exported from Altium, OrCAD, or other EDA tools, then explore components, nets, and pin-level connectivity. Multi-part components (ICs split into sections like U5A/U5B/U5C) are automatically detected and merged into a single logical component.

What you can ask

Once connected, talk to your assistant about the design in plain language — it picks the right tools and chains them. The following are real questions with real answers, captured from a live MCP session against the boards in testdata/ (BeagleBone Black and Marvell OpenRD):

🧑‍🔧 What is U5 pin GPIO2_1 connected to?

🤖 runs get_pin_net(component="U5A", pin="GPIO2_1"), get_component_pins(name="P8")

U5A pin GPIO2_1 sits on net GPIO2_1, and the only other connection is P8.34 — pin 34 of expansion header P8. So this GPIO goes straight out to the expansion connector with nothing else on it: no pulls, no series resistor, just SoC-to-header.

🧑‍🔧 Is the boot configuration pulled up or down by default?

🤖 runs list_nets(pattern="boot"), find_pull_resistors(), get_net(...)

This netlist doesn't use SYSBOOT net names — the AM3358 boot-strap balls appear as nets GPIO2_6 through GPIO2_13. Each of these eight lines has both a 100k pull-up to VDD_3V3A (R80–R87) and a 100k pull-down to DGND (R100–R107) — the classic stuffing-option pattern, so the actual boot word depends on which resistors are populated. The Ethernet PHY straps (MODE0/1/2, RMIISEL) have the same up/down pairs.

🧑‍🔧 Trace the connection between the CPU and the Ethernet PHY.

🤖 runs trace_path(from="U5", to="U15") — verbatim output (23 paths; excerpt):

Connections from U5 to U15 (23):
  U5A.NRESET_INOUT -- SYS_RESETn -- U15.NRST
  U5B.GPIO0_28 -- RMII1_TXD0 -- U15.TXD0
  U5B.GPIO0_0 -- MDIO_DATA -- U15.MDIO
  U5B.GPIO0_1 -- MDIO_CLK -- U15.MDC
  U5B.GPIO2_21 -- RMII1_RXD0 -- R135 -- MODE0 -- U15.MODE0
  U5B.GPIO3_3 -- RMII1_TXEN -- U15.TXEN
  U5B.GPIO3_9 -- RMII1_TXCLK -- R206 -- TXCLK -- U15.TXCLK
  U5B.GPIO0_29 -- U5_H18 -- R201 -- RMII1_REFCLK -- R200 -- RCLKIN -- U15.CLKIN
  ...

The trace covers the complete interface: the RMII data bus, the MDIO management pair (MDIO_DATA/MDIO_CLK), the reset line, the strap pins behind their series resistors, and the clock paths — see the clock question below for what those R200/R201 resistors are doing.

🧑‍🔧 How does the Ethernet PHY get its clock?

🤖 runs list_components(cell_type="lan"), get_component_pins(name="Y4"), trace_path(from="U5", to="U15"), get_net(...)

The LAN8710 PHY (U15) is clocked primarily by its own 25 MHz crystal Y4 (Suntsu ITEMP, 20 pF): Y4.1 → PHY_XTAL1 → R199 → RCLKIN → U15.CLKIN. The series resistors exist because there's an alternative: the trace above shows the AM3358 can drive a reference clock into the PHY instead — U5B.GPIO0_29 -- R201 -- RMII1_REFCLK -- R200 -- RCLKIN -- U15.CLKIN — so the clock source is resistor-selectable between the crystal and the SoC.

🧑‍🔧 Write a Linux device-tree node for the user LEDs on this board.

🤖 runs get_net(name="USR0") … get_net(name="USR3"), get_component_pins(name="Q1"), get_net(name="LEDAC"), get_net(name="LEDAA"), find_pull_resistors()

The four user LEDs hang off U5A.GPIO1_21–GPIO1_24 (nets USR0–USR3). Each GPIO drives the base of an RN1907 transistor (Q1/Q2) whose collector sinks the LED cathode, with the anode fed from VDD_LED through a 470 Ω resistor — so the LEDs are active-high — and 100k pull-downs (R116–R119) hold them off until the pins are configured:

leds {
    compatible = "gpio-leds";

    led-usr0 {
        label = "beaglebone:green:usr0";
        gpios = <&gpio1 21 GPIO_ACTIVE_HIGH>;
        default-state = "off";
    };
    /* u

... View full README on GitHub